1. Field of the Invention
The present invention generally relates to a method for forming flip chip bumps or UBM(under bump metallurgy) for a high speed copper interconnect chip, and more particularly to a method for forming flip chip bumps or UBMs of copper/nickel, copper/nickel/copper or etc., which are carried out by a subsequent process of electroless copper plating and electroless nickel plating on a copper I/O pad.
2. Description of the Related Art
In the rapidly changing electronics industry, as higher integrated and more complex semiconductor technology is continuously developing, endeavors for achieving a system having higher performance together with more miniaturized size are on the way. As the line width of a semiconductor device is gradually decreased, inner gate delay becomes smaller. However, RC delay caused by interconnections of the chips is gradually increasing.
At present, most metal wires employ Al/SiO2 structure, in which the aluminum layer contains copper of 0.5 wt % and formed by sputtering method. Aluminum has low resistivity and good adhesiveness to SiO2 and silicon, so it is most used for interconnection material of a silicon-based integrated circuit. However, aluminum has drawbacks that deposition of a dielectric thin film should be carried out at about 400 to 450xc2x0 C., since aluminum has low melting point of 660xe2x96xa1 and also low eutectic temperature of 577xc2x0 C. when mixed with silicon. Also, it has other problems such as electromigration, spiking, hillock, poor via hole filling, poor step coverage and etc. Therefore, in order to solve electromigration and spiking problems, a small amount of Cu, Ti, Si and etc. are introduced into the aluminum when depositing an aluminum layer. Also, in order to reduce contact resistance in gate, source and drain, silicide is used which is formed by which is formed by diffusing a metal component on SiO2.
Tungsten is widely used as another interconnection material for a silicon-based integrated circuit with a line width at most 1 micron, and has a thermal expansion coefficient similar to that of silicon. Tungsten is being researched and used for filling a contact hole or a via hole due to its applicability to a high temperature process and excellent filling capability in a structure having a high aspect ratio, even though it has a drawback of high resistivity compared to aluminum.
However, such an improvement on Al/SiO2 structured metal wire process may have limitations in enhancing chip speed. Therefore, interconnection material with lower resistance is being more important, and thus a copper interconnect technique is gaining more interest since copper has resistivity of 1.67 xcexcxcexa9-cm lower than that of aluminum of 2.66 xcexc-cm and excellent resistance to electromigration. When copper wire is used alone, efficiency in chip speed can be enhanced only in 50%. But, when a polymer material having a dielectric constant much lower than that of SiO2 is used together, speed enhancement up to 400% can be expected. Therefore, when copper and a lower-premittivity insulating polymer are used, the number of metal layers in a chip can be reduced effectively.
However, in an actually used electronics system, high integration of a system is not obtained by micro-miniaturizing and highly integrating chips only. Chips require interconnection and effective packaging to supply current for stable operation and to effectively radiate heat. In use, total delay of a system results from both on-chip delay and off-chip package delay. In a very high speed system, at least 50% of total delay is off-chip package delay, and about 80% of total delay is expected to be packaging delay in 2000""s considering current integration techniques. Therefore, in the package of a copper chip, a novel technique for copper chip interconnection is highly required to utilize advantages of copper interconnection in the maximum amount.
Current techniques for semiconductor chip interconnections include wire bonding, tape automated bonding(TAB) and flip chip technique. Among them, direct chip attach(DCA), chip size package(CSP) and multichip module(MCM) are being more important in necessity which utilize a high density interconnection flip chip technique. IBM developed the conventional flip chip technique to apply to the conventional aluminum pad formed on an inorganic substrate by using a high melting point solder, for example, 95% Pb-5% Sn during 1970s. At present, IBM, Motorola, Delco and Flip Chip Technology in the U.S.A. or Hitachi and Toshiba in Japan, and etc. are developing flip chip bumping techniques by using solder substance with low melting point to use organic substrates in low price.
However, the novel copper interconnect chip technique is in the initial stage of research and development in respect to the conventional aluminum interconnection. Also, presently research results for wire bonding or flip chip technique on a copper pad is not reported at all. These techniques will gain economic importance when the copper chip is generally used in the industry.
The present inventors, while studying a novel technique to substitute the conventional aluminum interconnection, found that copper/nickel bumps or UBMs which meet requirements of electronic devices can be formed by repeating electroless copper plating and electroless nickel plating which are relatively in low price in forming non-solder bumps or UBMs for enabling flip chip interconnection on a copper pad for high speed operation, thereby completing the present invention.
Therefore, it is an object of the present invention to provide a method for forming electroless copper/nickel bumps and UBMs of a copper interconnect which has excellent selectivity and adhering strength to a copper chip pad together with fast plating rate, and to adopt electroless plating in process stage, thereby by reducing process time and saving cost to enhance productivity.
According to the present invention, there is provided a method for forming flip chip bumps and under bump metallurgy for a high speed copper interconnect chip, the method comprising the steps of: (a) plating copper on a copper pad via electroless plating to form a copper plated layer; and (b) plating nickel on the copper plated layer via electroless plating to form a nickel plated layer.